The following reference describes a conventional DRAM:
Reference: 1992 Symposium on VLSI Circuits Digest of Technical Papers IEEE "A Boosted Dual Word-Line Decoding Scheme for 256 Mb DRAMs" P. 112-113 (K. Noda et al.)
The memory cell area of the conventional DRAM described in this reference is divided by a plurality of memory arrays. This DRAM is provided with a plurality of bit line couples and a plurality of word lines which are intersection-arranged on respective memory cell arrays. Each memory cell array is provided with word line drive circuits for driving the word lines. These word line drive circuits are provided along a plurality of memory arrays. In addition, this DRAM has sense amplifiers connected to a plurality of bit line couples. These sense amplifiers are provided in parallel with the word lines. Line decoders are provided along the word line drive circuits near this memory cell area. These line decoders are used to select the main word lines. A plurality of drive signal generating circuits are arranged concentrated at one-side ends of the word line drive circuits near the memory cell area. These drive signal generating circuits are for supplying the drive signals to a plurality of word line drive circuits.
In this DRAM, a main word line is selected by boosting one of the main word lines to a voltage VBOOT, which is higher than the power supply voltage VCC, by the line decoder. Thus the word line drive circuits connected to the selected main word line become ready to operate. A drive signal generating circuit operates in response to a specified address signal to supply a drive signal to the specified word line drive circuit. The word line drive circuits to which the drive signal is supplied boost the specified word lines connected thereto to the voltage VBOOT and the data stored in the memory cells connected to these word lines is outputted to the bit line couples.
Lately, semiconductor memories such as the DRAM have been demanded to provide higher operating speeds along with the increased storage capacities.
An object of the present invention is to provide a semiconductor memory which has implements high speed operation.